1. Field of the Invention
The present invention relates generally to the field of semiconductor manufacturing, and more particularly, to a copper/barrier chemical mechanical polishing (CMP) process.
2. Description of the Prior Art
In the process of fabricating integrated circuits, it is necessary to periodically planarize the wafer surface. One technique for planarizing the surface of a wafer is chemical mechanical polishing (CMP). In CMP processing, a wafer is placed face down on a rotating platen. The wafer, held in place by a carrier or polishing head, independently rotates about its own axis on the platen. Typically, the head is a floating polishing head with a flexible membrane. On the surface of the platen is a polishing pad over which there is dispensed a layer of aqueous polishing slurry. Ordinarily, the slurry chemistry, which is essential to proper polishing, consists of a colloidal solution of silica particles in a carrier solution.
Copper damascene or copper dual damascene technique combined with copper CMP are known in the art. In a conventional copper dual damascene process, a dielectric layer is deposited onto a substrate, patterned, and etched back such that trenches, vias, and other recessed regions etched into the dielectric layer represent the desired metal interconnection pattern. Barriers and copper are then sequentially deposited/sputtered over the entire surface of the device, filling the recessed regions and blanketing the surface of the dielectric layer. The bulk copper layer and barrier layer are then polished back to a degree such that the Cu/barrier structure becomes electrically isolated within the recessed regions etched out of the dielectric material. For reliability concerns, the aforesaid bulk copper layer is not removed or buffed off in one step, but usually in two steps with different removal rates, according to the prior art.
FIG. 1 depicts a cross-sectional view of a semiconductor wafer 10 having a typical dual damascene structure therein. As shown in FIG. 1, the dual damascene structure formed within a dielectric layer 20 is composed of via hole 22 and trench 23. A conductive layer or an underlying device 14 is formed in a dielectric layer 12 beneath via hole 22. A chemical mechanical polished copper layer 24 fills the trench 23 and via hole 22. A barrier layer 25 is disposed on interior surface of the dual damascene structure 11 to avoid copper diffusion, which usually causes a leakage current.
U.S. Pat. No. 6,573,173 to Farkas et al. discloses a method for forming a copper interconnection using a multi-platen CMP process. The method taught in this patent includes the steps of (1) forming an interconnect material comprising a top bulk metal layer and a lower barrier layer over a semiconductor substrate; (2) polishing an upper portion of the bulk metal layer at a first removal rate (at least 1000 angstroms per minute) using a first platen (ex. IC 1000 or IC 1010 from Rodel); (3) polishing remaining lower portion (<2000 angstroms) of the bulk metal layer using a second platen at a second removal rate that is smaller than the first removal rate; and (4) polishing the barrier layer using a third platen. According to this patent, the second platen is different from the first platen.
However, the prior art copper CMP process provided in U.S. Pat. No. 6,573,173 has some disadvantages. First, to avoid slurry cross-contamination, a wet cleaning process is recommended and is performed at a station located between the first platen and the second platen. Secondly, according to this patent, in order to maximize the throughput of the system, it is important to keep the polishing time of Step 1 approximately equal to the polishing time of Step 2, which just makes things complicated. A computer coupled to the CMP tool for monitoring polishing times of Step 1 and Step 2 is thus required to achieve the purpose of balancing the polishing times between the two polishing steps. Further, the use of high down force in Step 1 might cause crushing or scratching of the underlying porous low-k dielectrics. Moreover, when performing this prior art copper CMP process, at least three platens are required, which means additional maintenance fee and extra cost of parts.
In light of the foregoing, there is a constant need in this industry to provide an improved copper CMP process with sufficient reliability, increased throughput and relatively low cost.